Problem: multi-layer page table require multiple memory access
Observation: memory access are local
Solution: cache virtual to physical address translation (not data)

One instruction: can have multiple memory access
Look up next instruction
Stack pointer access and changing
Data fetch
Data store
Typical TLB size: 16~64 entries (bigger size = less efficient), and 2TLB (one for instruction, one for data) is common.
CPU Context Switch:
restore general purpose registers
restore page table base register (+length register)
flush TLB:
TLB Flush: when
declear new page directory (set %cr3 in x86) flush local TLB
INVLPG invalidate TLB for specific page
Software-loaded TLB: (more flexible design)
since OS knows all mapping and permission
we can let TLB miss generate exception, and let OS handle TLB refill (instead of hardware)
we can "not lose" certain TLB entires
we can make TLB faster if impose some constraints on program memory (e.g. same size, then we just do math)

Benifits:
error handling code can be loaded only when needed
tables can ba allocated larger than used
computer can run program larger than physical memory (as long as you don't need them at once), swapping can't do this
programs can launch faster
Sometimes, hardware exception can be fixed, othertimes it becomes software exception (illegal memory access)
Software handler: autostack
Page Fault: TLB miss and Page Table not present

Page Fault Handler:
refill page or kill process (if illegal access)
make "list of regions" happy by finding "list of pages"
Page Table might not be good data structure for page fault handler:
per-page nature is repetitive
disk sector address is 48 bits (> 32 bits)
per region methods: fault(), evict(), unmap()
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