Lecture 015

Address Space (2)

Translation Lookaside Buffer (TLB)

Problem: multi-layer page table require multiple memory access

Observation: memory access are local

Solution: cache virtual to physical address translation (not data)

TLB refill

TLB refill

One instruction: can have multiple memory access

Typical TLB size: 16~64 entries (bigger size = less efficient), and 2TLB (one for instruction, one for data) is common.

CPU Context Switch:

TLB Flush: when

Software-loaded TLB: (more flexible design)

The whole translation

The whole translation

Partial Memory Residence

Benifits:

Page Fault Handler

Sometimes, hardware exception can be fixed, othertimes it becomes software exception (illegal memory access)

Software handler: autostack

Page Fault: TLB miss and Page Table not present

Different section has different page fault handler. (not a read() syscall because it is slow, but we I/O block)

Different section has different page fault handler. (not a read() syscall because it is slow, but we I/O block)

Page Fault Handler:

Page Table might not be good data structure for page fault handler:

Table of Content